The technique disclosed herein relates to semiconductor integrated circuit devices, and more specifically, to a semiconductor integrated circuit device including an ESD protection circuit.
In recent years, with an improvement in the performance of semiconductor integrated circuits, the thickness of gate oxide films of transistors tends to be reduced in order to enhance the drivability of the transistors. The reduction in the thickness of the gate electrode films has reduced resistance to a breakdown caused by electrostatic discharge (ESD). In order to protect the semiconductor integrated circuits from the breakdown caused by the ESD, it has become important to provide ESD protection circuits. For example, when a semiconductor integrated circuit includes a plurality of power supply systems, such as the case where power supplies are separated between a digital circuit and an analog circuit in order to reduce noise propagation, and the case where power supplies are separated between a plurality of circuits in order to allow a stand-by state of some of the plurality of circuits, an ESD protection circuit is provided in each of the power supply systems.
In general, since the area of the ESD protection circuit is larger than that of a logic circuit, it becomes important to reduce an increase in the area of the ESD protection circuit. Therefore, Japanese Unexamined Patent Publication No. 2005-093497 describes an ESD protection circuit in which an abnormal current caused by a high voltage such as ESD can be quickly discharged, and the size of constituent elements is small. The ESD protection circuit uses an RC delay caused by a resistive element and a capacitive element.